[all-commits] [llvm/llvm-project] 6cfb64: AMDGPU: Minor updates to program resource register...

[Konstantin Zhuravlyov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cfb64276d47b6c24f85311ddcc80fa8d703d76b
      https://github.com/llvm/llvm-project/commit/6cfb64276d47b6c24f85311ddcc80fa8d703d76b
  Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
  Date:   2023-10-19 (Thu, 19 Oct 2023)

  Changed paths:
    M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
    A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
    M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s

  Log Message:
  -----------
  AMDGPU: Minor updates to program resource registers (#69525)

- Be explicit about which program resource register is supported by
which target
    - RSRC1
      - FP16_OVFL is GFX9+
      - WGP_MODE is GFX10+
      - MEM_ORDERED is GFX10+
      - FWD_PROGRESS is GFX10+
    - RSRC3
      - INST_PREF_SIZE is GFX11+
      - TRAP_ON_START is GFX11+
      - TRAP_ON_END is GFX11+
      - IMAGE_OP is GFX11+
  - Do not emit GFX11+ fields when disassembling GFX10 code objects
  - Tighten enforcement of reserved bits in disassembler

---------

Co-authored-by: Konstantin Zhuravlyov <kzhuravl at amd.com>