[all-commits] [llvm/llvm-project] d51855: [RISCV] Fix assertion failure from performBUILD_VE...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d51855f70034ecd3f356ea154dff96174f4a47a0
      https://github.com/llvm/llvm-project/commit/d51855f70034ecd3f356ea154dff96174f4a47a0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-18 (Wed, 18 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll

  Log Message:
  -----------
  [RISCV] Fix assertion failure from performBUILD_VECTORCombine when the binop is a shift. (#69349)

The RHS of a shift can have a different type than the LHS. If there are
undefs in the vector, we need the undef added to the RHS to match the
type of any shift amounts that are also added to the vector.

For now just don't add shifts if their RHS and LHS don't match.