[all-commits] [llvm/llvm-project] 040df1: [RISCV] Don't let performBUILD_VECTORCombine form ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 040df124a24234ec6e0cac9cf5434c6630cc6add
      https://github.com/llvm/llvm-project/commit/040df124a24234ec6e0cac9cf5434c6630cc6add
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-18 (Wed, 18 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Don't let performBUILD_VECTORCombine form a division or remainder with undef elements. (#69482)

Division/remainder by undef is immediate UB across the entire vector.