[all-commits] [llvm/llvm-project] 8a7010: [ARM] Lower i1 concat via MVETRUNC

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a701024f3e093c5f1cf6dd022f57baff0551a49
      https://github.com/llvm/llvm-project/commit/8a701024f3e093c5f1cf6dd022f57baff0551a49
  Author: David Green <david.green at arm.com>
  Date:   2023-10-18 (Wed, 18 Oct 2023)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/ARM/fadd-select-fneg-combine.ll
    M llvm/test/CodeGen/Thumb2/active_lane_mask.ll
    M llvm/test/CodeGen/Thumb2/mve-concat.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
    M llvm/test/CodeGen/Thumb2/mve-phireg.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

  Log Message:
  -----------
  [ARM] Lower i1 concat via MVETRUNC

The MVETRUNC operation can perform the same truncate of two vectors, without
requiring lane inserts/extracts from every vector lane. This moves the concat
i1 lowering to use it for v8i1 and v16i1 result types, trading a bit of extra
stack space for less instructions.