[all-commits] [llvm/llvm-project] f48dab: Add RV64 constraint to SRLIW (#69416)

[Shao-Ce SUN via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f48dab523784252448dbd42e72f0048ee0463368
      https://github.com/llvm/llvm-project/commit/f48dab523784252448dbd42e72f0048ee0463368
  Author: Shao-Ce SUN <sunshaoce at outlook.com>
  Date:   2023-10-18 (Wed, 18 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    A llvm/test/CodeGen/RISCV/aext.ll

  Log Message:
  -----------
  Add RV64 constraint to SRLIW (#69416)

Fixes #69408