[all-commits] [llvm/llvm-project] 041a78: [AArch64] Fix pairing different types of registers...

[Zhaoxuan Jiang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 041a786c78fbcee3537ca636bf796bb18fb6f313
      https://github.com/llvm/llvm-project/commit/041a786c78fbcee3537ca636bf796bb18fb6f313
  Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
  Date:   2023-10-16 (Mon, 16 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
    A llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-odd-csrs.ll

  Log Message:
  -----------
  [AArch64] Fix pairing different types of registers when computing CSRs. (#66642)

If a function has odd number of same type of registers to save, and the
calling convention also requires odd number of such type of CSRs, an FP
register would be accidentally marked as saved when producePairRegisters
returns true.

This patch also fixes the AArch64LowerHomogeneousPrologEpilog pass not
handling AArch64::NoRegister; actually this pass must be fixed along
with the register pairing so i can write a test for it.