[all-commits] [llvm/llvm-project] 9d1a3f: [RISCV][GISel] Add isel patterns for ADDIW/SRLIW/S...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d1a3fdd6278154fb4e7706419095ac7bfd72dcb
      https://github.com/llvm/llvm-project/commit/9d1a3fdd6278154fb4e7706419095ac7bfd72dcb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-13 (Fri, 13 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td

  Log Message:
  -----------
  [RISCV][GISel] Add isel patterns for ADDIW/SRLIW/SRAIW/SLLIW and remove custom selection. (#68470)

I had trouble getting patterns working previously because GISel was
using an i32 immediate, but the instructions expected an i64 immediate
because SelectionDAG doesn't have i32 as a legal type yet.

After looking at other targets like AMDGPU, I discovered that I could
use a SDNodeXForm and a cast to get the type checking in tablegen to
allow me to do it.