[all-commits] [llvm/llvm-project] 2c1f37: [test] precommit sched model for tsv110, NFC

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c1f37b3b95233c9e8eb9d51b50ac37640919eba
      https://github.com/llvm/llvm-project/commit/2c1f37b3b95233c9e8eb9d51b50ac37640919eba
  Author: zhongyunde 00443407 <zhongyunde at huawei.com>
  Date:   2023-10-12 (Thu, 12 Oct 2023)

  Changed paths:
    A llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-writeback.s

  Log Message:
  -----------
  [test] precommit sched model for tsv110, NFC


  Commit: d093aee1a33e006b31fe5962fa9f98d9c4507283
      https://github.com/llvm/llvm-project/commit/d093aee1a33e006b31fe5962fa9f98d9c4507283
  Author: zhongyunde 00443407 <zhongyunde at huawei.com>
  Date:   2023-10-12 (Thu, 12 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-writeback.s

  Log Message:
  -----------
  [AArch64] Fix schedmodel pre/post-index loads and stores for TSV110

Similar to D159254, this fixes the order of WriteAdr operands on
post/pre-inc loads/stores in the TSV110 scheduling model.


Compare: https://github.com/llvm/llvm-project/compare/30240e428f0e...d093aee1a33e