[all-commits] [llvm/llvm-project] f3c92a: [RISCV] Make PostRAScheduler a target feature (#68...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3c92a06b96a5302d4ed0a92c425efea7a41a16e
      https://github.com/llvm/llvm-project/commit/f3c92a06b96a5302d4ed0a92c425efea7a41a16e
  Author: Wang Pengcheng <137158460+wangpc-pp at users.noreply.github.com>
  Date:   2023-10-11 (Wed, 11 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll

  Log Message:
  -----------
  [RISCV] Make PostRAScheduler a target feature (#68692)

This is what AArch64 has done in https://reviews.llvm.org/D20762.

Tests are added in macro fusion tests, which uncover a bug that
DAG mutations don't take effect.