[all-commits] [llvm/llvm-project] 203ba2: [LoongArch] Improve codegen for atomic ops (#67391)

[hev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 203ba238e33c570dba6cbcf247f1668bb2a13c26
      https://github.com/llvm/llvm-project/commit/203ba238e33c570dba6cbcf247f1668bb2a13c26
  Author: hev <wangrui at loongson.cn>
  Date:   2023-10-11 (Wed, 11 Oct 2023)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
    M llvm/unittests/Target/LoongArch/InstSizes.cpp

  Log Message:
  -----------
  [LoongArch] Improve codegen for atomic ops (#67391)

This PR improves memory barriers generated by atomic operations.

Memory barrier semantics of LL/SC:
```
LL: <memory-barrier> + <load-exclusive>
SC: <store-conditional> + <memory-barrier>
```

Changes:
* Remove unnecessary memory barriers before LL and between LL/SC.
* Fix acquire semantics. (If the SC instruction is not executed, then
the guarantee of acquiring semantics cannot be ensured. Therefore, an
acquire barrier needs to be generated when memory ordering includes an
acquire operation.)