[all-commits] [llvm/llvm-project] 86d6b3: [RISCV][GlobalISel] Select G_ICMP, G_LOAD, G_STORE...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 86d6b379c43dcb4220a39bdf839b134474b7206d
      https://github.com/llvm/llvm-project/commit/86d6b379c43dcb4220a39bdf839b134474b7206d
  Author: Nitin John Raj <105745460+nitinjohnraj at users.noreply.github.com>
  Date:   2023-10-10 (Tue, 10 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

  Log Message:
  -----------
  [RISCV][GlobalISel] Select G_ICMP, G_LOAD, G_STORE, G_ZEXTLOAD (#67619)

We use tablegen patterns to select for G_ICMP. There are existing
SelectionDAG patterns for selecting G_LOAD, G_STORE and G_ZEXTLOAD with
XLenVT type data. We introduce GIAddrRegImm to successfully import those
patterns. For pointer and i32 loads and stores, we introduce new patterns, since these are not legal types in SelectionDAG.