[all-commits] [llvm/llvm-project] be81f4: [MLIR][Transforms] Fix Mem2Reg removal order to re...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: be81f42b551c8b3c520132c3d60bc19cfc1c72fb
      https://github.com/llvm/llvm-project/commit/be81f42b551c8b3c520132c3d60bc19cfc1c72fb
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2023-10-10 (Tue, 10 Oct 2023)

  Changed paths:
    M mlir/lib/Transforms/Mem2Reg.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][Transforms] Fix Mem2Reg removal order to respect dominance (#68687)

This commit fixes a bug in the Mem2Reg operation erasure order.
Replacing the topological order with a dominance based order ensures
that no operation is removed before all its uses have been replaced.
Additionally, the reliance on the `DenseMap` key order was eliminated by
switching to a `MapVector`, that gives a deterministic iteration order.

Example:

```
%ptr = alloca ...
...
%val0 = %load %ptr ... // LOAD0
store %val0 %ptr ...
%val1 = load %ptr ... // LOAD1
````

When promoting the slot backing %ptr, it can happen that the LOAD0 was
cleaned before LOAD1. This results in all uses of LOAD0 being replaced
by its reaching definition, before LOAD1's result is replaced by LOAD0's
result. The subsequent erasure of LOAD0 can thus not succeed, as it has
remaining usages.