[all-commits] [llvm/llvm-project] f5031c: [AArch64] Fix postinc operands for Cortex-A510 sch...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5031c655ddab72bdeccf5f830a17448926254e2
      https://github.com/llvm/llvm-project/commit/f5031c655ddab72bdeccf5f830a17448926254e2
  Author: David Green <david.green at arm.com>
  Date:   2023-10-10 (Tue, 10 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/ld1postmul.ll
    M llvm/test/CodeGen/AArch64/machine-cse-profitable-check.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s

  Log Message:
  -----------
  [AArch64] Fix postinc operands for Cortex-A510 scheduling

Similar to D159254, this fixes the order of WriteAdr operands on post/pre-inc
loads/stores in the Cortex-A510 scheduling model.

I will add the same for other models too, this will be the most impactful due
to it being the default cpu scheduling model.

Closes #68518