[all-commits] [llvm/llvm-project] ee9f96: [RISCV][GISel] Add FPR register bank.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ee9f96bdd115e1e726e2708d791530c4d686dad2
      https://github.com/llvm/llvm-project/commit/ee9f96bdd115e1e726e2708d791530c4d686dad2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td

  Log Message:
  -----------
  [RISCV][GISel] Add FPR register bank.

We need this so isel can use getRegBankFromRegClass to disambiguate
FSW and SW patterns without depending on pattern order in the tablegen
source files.

While there, add a few missing GPR register classes and sort them
in the order they appear in the tblgen output file.