[all-commits] [llvm/llvm-project] 6afceb: [AMDGPU][IGLP] SingleWaveOpt: Cache DSW Counters f...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6afceba5106a2a5eb229791465d53ca4be257d5b
      https://github.com/llvm/llvm-project/commit/6afceba5106a2a5eb229791465d53ca4be257d5b
  Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir

  Log Message:
  -----------
  [AMDGPU][IGLP] SingleWaveOpt: Cache DSW Counters from PreRA (#67759)

Save the DSW counters from PreRA scheduling. While this avoids recalculation in the postRA pass, that isn't the main purpose.

This is required because of physical register dependencies in PostRA scheduling -- they alter the DAG s.t. our counters may become incorrect -- which alters the layout of the pipeline. By preserving the values from PreRA, we can be sure that we accurately construct the pipeline.

Additionally, remove a bad assert in SharesPredWithPrevNthGroup -- it is possible that we will have an empty cache if OtherGroup has no elements which have a V_PERM pred (possible if the V_PERM SG is empty).