[all-commits] [llvm/llvm-project] 862407: [RISCV] Strip W suffix from ADDIW (#68425)

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 862407510595e37266e3dc0df6a00cad78f420bf
      https://github.com/llvm/llvm-project/commit/862407510595e37266e3dc0df6a00cad78f420bf
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/add-before-shl.ll
    M llvm/test/CodeGen/RISCV/add-imm.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/and.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/bfloat.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
    M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
    M llvm/test/CodeGen/RISCV/rvv/select-sra.ll
    M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/select-to-and-zext.ll
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shl-demanded.ll
    M llvm/test/CodeGen/RISCV/shlimm-addimm.ll
    M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ only due to the use of addi on rv32 vs addiw on rv64 when the
high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate
restriction on the compressed variants because we're not directly
forming the compressed variants. If we happen to get a zero immediate
for the ADDI, then either a later optimization will strip the useless
instruction or the encoder is responsible for not compressing the
instruction.