[all-commits] [llvm/llvm-project] ccf68a: Revert "MachineSink: Fix sinking VGPR def out of a...

[petar-avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ccf68ab4322962981f71114567c19f7d692f9e06
      https://github.com/llvm/llvm-project/commit/ccf68ab4322962981f71114567c19f7d692f9e06
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir

  Log Message:
  -----------
  Revert "MachineSink: Fix sinking VGPR def out of a divergent loop"

This reverts commit 3f8ef57bede94445b1a1042c987cc914a886e7ff.


  Commit: 2d7fe90a3eb8b31bc02ee4407b3e74336ac729fc
      https://github.com/llvm/llvm-project/commit/2d7fe90a3eb8b31bc02ee4407b3e74336ac729fc
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/machine-sink-lane-mask.mir
    A llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    A llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir

  Log Message:
  -----------
  AMDGPU: Add test for temporal divergence introduced by machine-sink

Introduced by 5b657f50b8e8dc5836fb80e566ca7569fd04c26f that moved
LICM after AMDGPUCodeGenPrepare. Some instructions are no longer
sunk during ir optimizations but in machine-sinking instead.
If vgpr instruction used sgpr defined inside the cycle is sunk outside
of the cycle we end up with not-handled case of temporal divergence.
Add test for theoretical case when SALU instruction (represents
uniform value) is sunk outside of the cycle.
Add a test when SALU instruction can be sunk if it edits lane mask.


  Commit: 2fa7d652d02ae5da0d32d63c4258705eadab1576
      https://github.com/llvm/llvm-project/commit/2fa7d652d02ae5da0d32d63c4258705eadab1576
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2023-10-06 (Fri, 06 Oct 2023)

  Changed paths:
    M llvm/include/llvm/ADT/GenericCycleImpl.h
    M llvm/include/llvm/ADT/GenericCycleInfo.h
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir

  Log Message:
  -----------
  AMDGPU: Fix temporal divergence introduced by machine-sink (#67456)

Temporal divergence that was present in input or introduced in IR
transforms, like code-sinking or LICM, is handled in SIFixSGPRCopies
by changing sgpr source instr to vgpr instr.
After 5b657f5, that moved LICM after AMDGPUCodeGenPrepare,
machine-sinking can introduce temporal divergence by sinking
instructions outside of the cycle.
Add isSafeToSink callback in TargetInstrInfo.


Compare: https://github.com/llvm/llvm-project/compare/b3b3336e8276...2fa7d652d02a