[all-commits] [llvm/llvm-project] 3c0990: [RISCV] Generalize the (ADD (SLLI X, 32), X) speci...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c0990c188e97086dec70ce1a36729f236f86093
      https://github.com/llvm/llvm-project/commit/3c0990c188e97086dec70ce1a36729f236f86093
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-02 (Mon, 02 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

  Log Message:
  -----------
  [RISCV] Generalize the (ADD (SLLI X, 32), X) special case in constant materialization. (#66931)

We don't have to limit ourselves to a shift amount of 32. We can support
other shift amounts that make the upper 32 bits line up.