[all-commits] [llvm/llvm-project] 8f2ffb: [lldb][AArch64] Add type marker to ReadAll/WriteAL...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f2ffb1cf31fffda0e139dd8afeb02f4001745e5
      https://github.com/llvm/llvm-project/commit/8f2ffb1cf31fffda0e139dd8afeb02f4001745e5
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2023-09-11 (Mon, 11 Sep 2023)

  Changed paths:
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
    M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

  Log Message:
  -----------
  [lldb][AArch64] Add type marker to ReadAll/WriteALLRegisterValues data

While working in support for SME's ZA register, I found a circumstance
where restoring ZA after SVE, when the current SVE mode is non-streaming,
will kick the process back into FPSIMD mode. Meaning the SVE values that
you just wrote are now cut off at 128 bit.

The fix for that is to write ZA then SVE. Problem with that
is, the current ReadAll/WriteAll makes a lot of assumptions about the
saved data length.

This patch changes the format so there is a "type" written before
each data block. This tells WriteAllRegisterValues what it's looking at
without brittle checks on length, or assumptions about ordering.

If we want to change the order of restoration, all we now have to
do is change the order of saving.

This exposes a bug where the TLS registers are not restored.
This will be fixed by https://reviews.llvm.org/D156512 in some form,
depending on what lands first.

Existing SVE tests certainly check restoration and when I got this
wrong, many, many tests failed. So I think we have enough coverage
already, and more will be coming with future ZA changes.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D156687