[all-commits] [llvm/llvm-project] 4d2536: [RISCV] Enable more builtin for zvfhmin without zvfh

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d2536c82fc426f0e622a09c0a3e048a0c734f3d
      https://github.com/llvm/llvm-project/commit/4d2536c82fc426f0e622a09c0a3e048a0c734f3d
  Author: Jianjian GUAN <jacquesguan at me.com>
  Date:   2023-09-08 (Fri, 08 Sep 2023)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

  Log Message:
  -----------
  [RISCV] Enable more builtin for zvfhmin without zvfh

This patch enables some fp16 vector type builtins that don't use fp arithmetic instruction for zvfhmin without zvfh.
Include following builtins:
  vector load/store,
  vector reinterpret,
  vmerge_vvm,
  vmv_v.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151869