[all-commits] [llvm/llvm-project] c39b50: [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 V...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c39b50444cc5c9e3d1e370d1899723251e0befa1
      https://github.com/llvm/llvm-project/commit/c39b50444cc5c9e3d1e370d1899723251e0befa1
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-09-07 (Thu, 07 Sep 2023)

  Changed paths:
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s

  Log Message:
  -----------
  [RISCV][llvm-mca] Add llvm-mca tests for SiFive7 Vector Integer Arith… (#65283)

…metic

The intention of this test file long term is to test all valid (LMUL,
SEW) pairs for each SchedWrite class. For this reason, we do not test
every single instruction under every (LMUL, SEW) pair, since multiple
instructions may use the same SchedWrite. For example, vadd.vv and
vsub.vv both use the WriteVIALUV class.

I didn't end up getting all (LMUL, SEW) pair for each SchedWrite class
though. For example, vadd.vv and vadd.vx use WriteVIALUV and WriteVIALUX
respectivley, but I treated all Vector Single-Width Integer Add and
Subtract instructions as having the same behavior. I plan on improving
the coverage as time goes on and figured this would be a good start. If
there is any class of vector integer arithmetic instructions you'd like
to see full coverage for in this patch, please let me know.