[all-commits] [llvm/llvm-project] 7dd48c: [X86][RFC] Add new option `-m[no-]evex512` to disa...

[Phoebe Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7dd48cc24de2d54d40527432cbee8a9d97a8a4f7
      https://github.com/llvm/llvm-project/commit/7dd48cc24de2d54d40527432cbee8a9d97a8a4f7
  Author: Phoebe Wang <phoebe.wang at intel.com>
  Date:   2023-09-07 (Thu, 07 Sep 2023)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/include/clang/Driver/Options.td
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Basic/Targets/X86.h
    M clang/lib/CodeGen/Targets/X86.cpp
    M clang/lib/Headers/avx512bf16intrin.h
    M clang/lib/Headers/avx512bitalgintrin.h
    M clang/lib/Headers/avx512bwintrin.h
    M clang/lib/Headers/avx512cdintrin.h
    M clang/lib/Headers/avx512dqintrin.h
    M clang/lib/Headers/avx512fintrin.h
    M clang/lib/Headers/avx512fp16intrin.h
    M clang/lib/Headers/avx512ifmaintrin.h
    M clang/lib/Headers/avx512vbmi2intrin.h
    M clang/lib/Headers/avx512vbmiintrin.h
    M clang/lib/Headers/avx512vnniintrin.h
    M clang/lib/Headers/avx512vp2intersectintrin.h
    M clang/lib/Headers/avx512vpopcntdqintrin.h
    M clang/lib/Headers/gfniintrin.h
    M clang/lib/Headers/vaesintrin.h
    A clang/test/CodeGen/X86/avx512-error.c
    M clang/test/CodeGen/attr-cpuspecific.c
    M clang/test/CodeGen/attr-target-x86.c
    M clang/test/CodeGen/regcall2.c
    M clang/test/CodeGen/target-avx-abi-diag.c
    M clang/test/Driver/x86-target-features.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86Subtarget.cpp
    M llvm/lib/Target/X86/X86Subtarget.h
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/X86/avx512bwvl-arith.ll
    M llvm/test/CodeGen/X86/avx512vl-arith.ll

  Log Message:
  -----------
  [X86][RFC] Add new option `-m[no-]evex512` to disable ZMM and 64-bit mask instructions for AVX512 features

This is an alternative of D157485 and a pre-feature to support AVX10.

AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267
AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343
RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661

Based on the feedbacks from LLVM and GCC community, we have agreed to
start from supporting `-m[no-]evex512` on existing AVX512 features.
The option `-mno-evex512` can be used with `-mavx512xxx` to build
binaries that can run on both legacy AVX512 targets and AVX10-256.

There're still arguments about what's the expected behavior when this
option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We
decided to defer the support of `-mavx10.1` after we made consensus.
Or furthermore, we start from supporting AVX10.2 and not providing any
AVX10.1 options.

Reviewed By: RKSimon, skan

Differential Revision: https://reviews.llvm.org/D159250