[all-commits] [llvm/llvm-project] db5d84: [NVPTX] Make i16x2 a native type and add supported...

[Thomas via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db5d845c73ee2d64f1a5bab3fc72edece9e3a7ba
      https://github.com/llvm/llvm-project/commit/db5d845c73ee2d64f1a5bab3fc72edece9e3a7ba
  Author: Thomas <thomas.raoux at openai.com>
  Date:   2023-09-06 (Wed, 06 Sep 2023)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
    M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
    M llvm/lib/Target/NVPTX/NVPTXUtilities.h
    M llvm/test/CodeGen/NVPTX/dag-cse.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    A llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
    M llvm/test/CodeGen/NVPTX/param-load-store.ll
    M llvm/test/CodeGen/NVPTX/vec-param-load.ll
    R llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intrinsic-inseltpoison.ll
    R llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intrinsic.ll
    A llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll

  Log Message:
  -----------
  [NVPTX] Make i16x2 a native type and add supported vec instructions (#65432)

On sm_90 some instructions now support i16x2 which allows hardware to
execute more efficiently add, min and max instructions.

In order to support that we need to make i16x2 a native type in the
backend. This does the necessary changes to make i16x2 a native type and
adds support for the instructions natively supporting i16x2.

This caused a negative test in nvptx slp to start passing. Changed the
test to a positive one as the IR is correctly vectorized.