[all-commits] [llvm/llvm-project] b027ce: [DAG] Fold (shl (sext (add_nsw x, c1)), c2) -> (ad...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b027ce0ab93060bc6cb79d5402d21520e8b93fb7
      https://github.com/llvm/llvm-project/commit/b027ce0ab93060bc6cb79d5402d21520e8b93fb7
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-09-06 (Wed, 06 Sep 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
    M llvm/test/CodeGen/AArch64/arm64-trunc-store.ll
    M llvm/test/CodeGen/X86/addr-mode-matcher-2.ll

  Log Message:
  -----------
  [DAG] Fold (shl (sext (add_nsw x, c1)), c2) -> (add (shl (sext x), c2), c1 << c2)

Assuming the ADD is nsw then it may be sign-extended to merge with a SHL op in a similar fold to the existing (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) fold.

This is most useful for helping to expose address math for X86, but has also touched several aarch64 test cases as well.

Alive2: https://alive2.llvm.org/ce/z/2UpSbJ

Differential Revision: https://reviews.llvm.org/D159198