[all-commits] [llvm/llvm-project] 2f3a36: [SPARC][IAS] Add v9 encoding of %fq

[Koakuma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f3a362cc06eb3f08bedd24d963cd892a01f9e72
      https://github.com/llvm/llvm-project/commit/2f3a362cc06eb3f08bedd24d963cd892a01f9e72
  Author: Koakuma <koachan at protonmail.com>
  Date:   2023-09-05 (Tue, 05 Sep 2023)

  Changed paths:
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    M llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
    M llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
    M llvm/test/MC/Sparc/sparcv9-instructions.s

  Log Message:
  -----------
  [SPARC][IAS] Add v9 encoding of %fq

While both SPARCv7/v8 and v9 has a register named %fq, they encode it
differently, so we need to differentiate between them.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D157232


  Commit: af70618e968f17e6c91c425db8bc52bdc81c3a45
      https://github.com/llvm/llvm-project/commit/af70618e968f17e6c91c425db8bc52bdc81c3a45
  Author: Koakuma <koachan at protonmail.com>
  Date:   2023-09-05 (Tue, 05 Sep 2023)

  Changed paths:
    M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
    M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h
    M llvm/lib/Target/Sparc/SparcInstr64Bit.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    A llvm/test/MC/Disassembler/Sparc/sparc-mem-v9.txt
    M llvm/test/MC/Sparc/sparc-atomic-instructions.s
    A llvm/test/MC/Sparc/sparc-mem-asi-instructions.s
    M llvm/test/MC/Sparc/sparc-mem-instructions.s
    M llvm/test/MC/Sparc/sparcv9-atomic-instructions.s
    M llvm/test/MC/Sparc/sparcv9-instructions.s

  Log Message:
  -----------
  [SPARC][IAS] Add complete set of v9 ASI load, store & swap forms

This extends support for ASI-tagged loads, stores, and swaps with the new
stored-ASI form ([reg+imm] %asi) introduced in v9.

CAS instructions are handled differently by the (dis-)assembler, so it will be
handled in a separate patch.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D157233


  Commit: f1246e90c023007e2f388787160dbe9234b203fc
      https://github.com/llvm/llvm-project/commit/f1246e90c023007e2f388787160dbe9234b203fc
  Author: Koakuma <koachan at protonmail.com>
  Date:   2023-09-05 (Tue, 05 Sep 2023)

  Changed paths:
    M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
    M llvm/lib/Target/Sparc/SparcInstr64Bit.td
    M llvm/lib/Target/Sparc/SparcInstrFormats.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    A llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
    M llvm/test/MC/Sparc/leon-instructions.s
    A llvm/test/MC/Sparc/sparc-cas-instructions.s
    M llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

  Log Message:
  -----------
  [SPARC][IAS] Add support for the full set of CAS instructions

This completes the support for the CAS instructions.

Besides the base CASA and CASXA forms, on v9 the aliases CAS, CASX, CASL, and
CASXL are also available.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D157234


Compare: https://github.com/llvm/llvm-project/compare/c6ce32d9c348...f1246e90c023