[all-commits] [llvm/llvm-project] 319aba: [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32...

Craig Topper via All-commits all-commits at lists.llvm.org
Thu Aug 31 20:25:05 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 319aba645f6a541f6c9f3f4cdb5775d7302d9df9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

If the high and low 32 bits are the same, we try to use
(ADD X, (SLLI X, 32)) but that only works if bit 31 is clear since
the low 32 bits will be sign extended.

If we have Zba we can use add.uw to zero the sign extended bits.

Reviewed By: reames, wangpc

Differential Revision: https://reviews.llvm.org/D159253

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