[all-commits] [llvm/llvm-project] 1664eb: [RISCV] Fix crash during during i1 vector bitrever...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1664eb05d0d335c7624e463d391beae8e32d74ba
      https://github.com/llvm/llvm-project/commit/1664eb05d0d335c7624e463d391beae8e32d74ba
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll

  Log Message:
  -----------
  [RISCV] Fix crash during during i1 vector bitreverse lowering

A shuffle of v256i1 with a large enough minimum vlen might make it through type
legalization and into lowering. In this case, zvl1024b was enough. The
bitreverse shuffle lowering would then try to convert this to a v1i256 type
which is invalid (v1i128 exists though, which is why the existing v128i1 tests
were fine).

This patch checks to make sure that the new type is not only legal but also
valid.

Reviewed By: craig.topper, reames

Differential Revision: https://reviews.llvm.org/D159215