[all-commits] [llvm/llvm-project] 64da98: [AArch64][SME] Add support for Copy/Spill/Fill of ...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 64da981b8b259c18313560bf629e1a8b3b7c1d52
      https://github.com/llvm/llvm-project/commit/64da981b8b259c18313560bf629e1a8b3b7c1d52
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir
    M llvm/test/CodeGen/AArch64/sve-copy-zprpair.mir

  Log Message:
  -----------
  [AArch64][SME] Add support for Copy/Spill/Fill of strided ZPR2/ZPR4 registers.

This patch contains a few changes:

* It changes the alignment of the strided/contiguous ZPR2/ZPR4 registers to
  128-bits. This is important, because when we spill these registers to the
  stack, the address doesn't need to be 256/512 bits aligned because we
  split the single-store/reload pseudo instruction up into multiple
  STR_ZXI/LDR_ZXI (single vector store/load) instructions, which only
  require a 128-bit alignment. Additionally, an alignment larger than the
  stack-alignment is not supported for scalable vectors.

* It adds support for these register classes in storeRegToStackSlot,
  loadRegFromStackSlot and copyPhysReg.

* It adds tests only for the strided forms. There is no need to also
  test the contiguous forms, because a register such as z2_z3 or
  z4_z5_z6_z7 are also part of the regular ZPR2 and ZPR4 register classes,
  respectively, which are already covered and tested.

Reviewed By: dtemirbulatov

Differential Revision: https://reviews.llvm.org/D159189