[all-commits] [llvm/llvm-project] a61c4a: [RISCV][SelectionDAG] Lower shuffles as bitrotates...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a61c4a0ef6f93fe21df5c40c5c45fc484d5e83e0
      https://github.com/llvm/llvm-project/commit/a61c4a0ef6f93fe21df5c40c5c45fc484d5e83e0
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M llvm/include/llvm/IR/Instructions.h
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

  Log Message:
  -----------
  [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

Given a shuffle mask like <3, 0, 1, 2, 7, 4, 5, 6> for v8i8, we can
reinterpret it as a shuffle of v2i32 where the two i32s are bit rotated, and
lower it as a vror.vi (if legal with zvbb enabled).
We also need to make sure that the larger element type is a valid SEW, hence
the tests for zve32x.

X86 already did this, so I've extracted the logic for it and put it inside
ShuffleVectorSDNode so it could be reused by RISC-V. I originally tried to add
this as a generic combine in DAGCombiner.cpp, but it ended up causing worse
codegen on X86 and PPC.

Reviewed By: reames, pengfei

Differential Revision: https://reviews.llvm.org/D157417


  Commit: 976244bb845ca6e59139fffdf0372e4aba962ff1
      https://github.com/llvm/llvm-project/commit/976244bb845ca6e59139fffdf0372e4aba962ff1
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

  Log Message:
  -----------
  [RISCV] Canonicalize vrot{l,r} to vrev8 when lowering shuffle as rotate

A rotate of 8 bits of an e16 vector in either direction is equivalent to a
byteswap, i.e. vrev8. There is a generic combine on ISD::ROT{L,R} to
canonicalize these rotations to byteswaps, but on fixed vectors they are
legalized before they have the chance to be combined. This patch teaches the
rotate vector_shuffle lowering to emit these rotations as byteswaps to match
the scalable vector behaviour.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D158195


Compare: https://github.com/llvm/llvm-project/compare/4a5bcbd5602b...976244bb845c