[all-commits] [llvm/llvm-project] 23fef2: [RISCV] Correct scheduling information for WriteVI...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 23fef2cc673a29afdd334eff70aef1adf73322d2
      https://github.com/llvm/llvm-project/commit/23fef2cc673a29afdd334eff70aef1adf73322d2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D159029