[all-commits] [llvm/llvm-project] 538b90: [RISCV][GlobalISel] Select ALU GPR instructions

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 538b90cf4c63c7f7b55a9eb9812e951529abd66c
      https://github.com/llvm/llvm-project/commit/538b90cf4c63c7f7b55a9eb9812e951529abd66c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    A llvm/lib/Target/RISCV/RISCVGISel.td
    A llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

  Log Message:
  -----------
  [RISCV][GlobalISel] Select ALU GPR instructions

Some instruction selection patterns required for ALU GPR instructions have already been automatically imported from existing TableGen descriptions - this patch simply adds testing for them. Logic for selecting constants and copies has been added, along with the first of the GIComplexPatternEquiv definitions required to select the shiftMaskXLen ComplexPattern. New patterns have been added to directly select RV64 W instructions from gMIR rather than using custom gMIR operations earlier in the pipeline. In future this could also support the checks present in the DAGToDAGISel for finding ops whose users only require the lower 32 bits.

Differential Revision: https://reviews.llvm.org/D76445


  Commit: ff6d33382faf3709fa270ae0abb8d165142df9ae
      https://github.com/llvm/llvm-project/commit/ff6d33382faf3709fa270ae0abb8d165142df9ae
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
    A llvm/test/CodeGen/RISCV/pr65025.ll

  Log Message:
  -----------
  [RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.

This disables the transform if the branch does not have the kill
flag set for the AND we want to delete.

Ideally we'd be able to share the AND with the AND we create in
the expansion, but that's a more complex transform. So this starts
with the simple approach to fix miscompile.

This should be backported to LLVM 17.

Fixes PR65025.ll

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D158962


Compare: https://github.com/llvm/llvm-project/compare/2102ed0b917b...ff6d33382faf