[all-commits] [llvm/llvm-project] 83f549: [BOLT] BL/BH are considered aliases in regreassign

[llongint via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 83f5497155e1d37c9b08447a2225a789095d53b0
      https://github.com/llvm/llvm-project/commit/83f5497155e1d37c9b08447a2225a789095d53b0
  Author: hezuoqiang <hezuoqiang2 at huawei.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M bolt/lib/Passes/RegReAssign.cpp
    A bolt/test/runtime/X86/reg-reassign-no-swap-bl.s

  Log Message:
  -----------
  [BOLT] BL/BH are considered aliases in regreassign

The relationship of X86 registers is shown in the diagram. BL and BH do
not have a direct alias relationship. However, if the BH register cannot be
swapped, then the BX/EBX/RBX registers cannot be swapped as well, which
means that BL register also cannot be swapped. Therefore, in the presence
of BX/EBX/RBX registers, BL and BH have an alias relationship.

    ┌────────────────┐
    │  RBX           │
    ├────┬───────────┤
    │    │ EBX       │
    ├────┴──┬────────┤
    │       │   BX   │
    ├───────┼───┬────┤
    │       │BH │BL  │
    └───────┴───┴────┘

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D155098