[all-commits] [llvm/llvm-project] 6e4860: [SDAG] Add SimplifyDemandedBits support for ISD::S...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e4860f5d028e03419ec7d5d2e6127d3a57df050
      https://github.com/llvm/llvm-project/commit/6e4860f5d028e03419ec7d5d2e6127d3a57df050
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/WebAssembly/pr59626.ll

  Log Message:
  -----------
  [SDAG] Add SimplifyDemandedBits support for ISD::SPLAT_VECTOR

This improves some cases where a splat_vector uses a build_pair that can be
simplified, e.g:

(rotl x:i64, splat_vector (build_pair x1:i32, x2:i32))

rotl only demands the bottom 6 bits, so this patch allows it to simplify it to:

(rotl x:i64, splat_vector (build_pair x1:i32, undef:i32))

Which in turn improves some cases where a splat_vector_parts is lowered on
RV32.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D158839


  Commit: 8f1d1e2b615b7924ed178f10fe94ad3f36415f0c
      https://github.com/llvm/llvm-project/commit/8f1d1e2b615b7924ed178f10fe94ad3f36415f0c
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-28 (Mon, 28 Aug 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

  Log Message:
  -----------
  [SDAG] Add computeKnownBits support for ISD::SPLAT_VECTOR_PARTS

We can work out the known bits for a given lane by concatenating the known bits of each scalar operand.

In the description of ISD::SPLAT_VECTOR_PARTS in ISDOpcodes.h it says that the
total size of the scalar operands must cover the output element size, but I've
added a stricter assertion here that the total width of the scalar operands
must be exactly equal to the element size. It doesn't seem to trigger, and I'm
not sure if there any targets that use SPLAT_VECTOR_PARTS for anything other
than v4i32 -> v2i64 splats.

We also need to include it in isTargetCanonicalConstantNode, otherwise
returning the known bits introduces an infinite combine loop.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158852


Compare: https://github.com/llvm/llvm-project/compare/5ade434a7e74...8f1d1e2b615b