[all-commits] [llvm/llvm-project] ca10a6: [X86] Add test coverage for min/max signbit simpli...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ca10a6caee412ee28cb18d5a5afd843ae3a7c823
      https://github.com/llvm/llvm-project/commit/ca10a6caee412ee28cb18d5a5afd843ae3a7c823
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-08-20 (Sun, 20 Aug 2023)

  Changed paths:
    M llvm/test/CodeGen/X86/combine-smax.ll
    M llvm/test/CodeGen/X86/combine-smin.ll
    M llvm/test/CodeGen/X86/combine-umax.ll
    M llvm/test/CodeGen/X86/combine-umin.ll

  Log Message:
  -----------
  [X86] Add test coverage for min/max signbit simplification

If we're only demanding the signbit from a min/max then we can simplify this to a logic op


  Commit: 95865e5138e2b69e371c334bbe945f673c30b24f
      https://github.com/llvm/llvm-project/commit/95865e5138e2b69e371c334bbe945f673c30b24f
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-08-20 (Sun, 20 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/combine-smax.ll
    M llvm/test/CodeGen/X86/combine-smin.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

Alive2: https://alive2.llvm.org/ce/z/MehvFB

REAPPLIED from 54d663d5896008 with fix for using the correct DemandedBits mask.


Compare: https://github.com/llvm/llvm-project/compare/96377e5cc1e3...95865e5138e2