[all-commits] [llvm/llvm-project] 770be4: [DAG] Fold insert_subvector undef, (extract_subvec...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 770be43f6782dab84d215d01b37396d63a9c2b6e
      https://github.com/llvm/llvm-project/commit/770be43f6782dab84d215d01b37396d63a9c2b6e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-18 (Fri, 18 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/X86/pr33349.ll
    M llvm/test/CodeGen/X86/pr34177.ll
    M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll

  Log Message:
  -----------
  [DAG] Fold insert_subvector undef, (extract_subvector X, 0), 0 with non-matching types

We have an existing DAG combine for when an insert/extract subvector pair is entirely a nop, but we hadn't handled the case where the net result was either an insert or an extract (but not both).  The transform is restricted to index = 0 to avoid having to adjust indices after the transform.

Reviews, a couple comments on the test changes:
* Mostly RISCV, mostly schedule reordering.
* One real regression in splats-with-mixed-vl.ll due to a different overly aggressive combine, fix in a follow up patch.
* The test/CodeGen/X86/vector-replicaton-i1-mask.ll diff looked concerning at first, but not the mask size at most 4 i1s.  I think the type changes on the mask loads are correct, but would welcome a second opinion with someone more familiar with AVX512 codegen.

Differential Revision: https://reviews.llvm.org/D158201


  Commit: 0a5347f40d8a5298d8815076ce85bf5de58083b5
      https://github.com/llvm/llvm-project/commit/0a5347f40d8a5298d8815076ce85bf5de58083b5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-08-18 (Fri, 18 Aug 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/umax.ll
    M llvm/test/CodeGen/X86/umin.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - Use DemandedBits intead of OriginalDemandedBits to when simplifying UMIN/UMAX to AND/OR.

DemandedBits is forced to all ones if there are multiple users.

The changes X86 test cases looks like they were miscompiles before.
The value of eax/rax from the cmov is returned from the function in
addition to being used by the sar. That usage needs all bits even
though the sar doesn't.


Compare: https://github.com/llvm/llvm-project/compare/160ab99539a1...0a5347f40d8a