[all-commits] [llvm/llvm-project] b5c106: [RISCV][GlobalISel] Legalize division and remainder

Nitin John Raj via All-commits all-commits at lists.llvm.org
Thu Aug 17 14:42:13 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5c106e873f780b2f54fec9817acfd252724bcb3
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-08-17 (Thu, 17 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-div.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-rem.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir

  Log Message:
  [RISCV][GlobalISel] Legalize division and remainder

Legalize division and remainder. We test for (s7, s8, s16, s32, s48, s64) on rv64 and (s8, s15, s16, s32, s64, s72, s128) on rv64, with and without the +m, +zmmul extensions. We do not handle types with size > 2 x XLen -- these ought to be handled in the IR pass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157422

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