[all-commits] [llvm/llvm-project] 638865: [RISCV][GlobalISel] Legalize multiplication

Nitin John Raj via All-commits all-commits at lists.llvm.org
Thu Aug 17 13:00:26 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 638865c8f93989c5f7a237417356c920d55e0136
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-08-17 (Thu, 17 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul.mir

  Log Message:
  [RISCV][GlobalISel] Legalize multiplication

Legalize multiplication with the +m, +zmmul extensions and without extensions. With extensions, we test for (s7, s8, s16, s32, s48, s64, s96) on rv32 and (s8, s15, s32, s64, s72, s128, s192) on rv64. Without extensions, test (s7, s8, s16, s32) on rv32 and (s8, s15, s16, s32, s64) on rv64. Does not yet work for the type which is 2 times XLen without extensions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157416

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