[all-commits] [llvm/llvm-project] 81827f: [AMDGPU] Support wwm-reg AV spill pseudos

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81827f8cfb223b2e0ba654ba6c838418d6cb67e5
      https://github.com/llvm/llvm-project/commit/81827f8cfb223b2e0ba654ba6c838418d6cb67e5
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2023-08-17 (Thu, 17 Aug 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir

  Log Message:
  -----------
  [AMDGPU] Support wwm-reg AV spill pseudos

The wwm register spill pseudos are currently defined for VGPR_32
regclass. It causes a verifier error for gfx908 or above as the
regalloc sometimes restores the values to the vector superclass AV_32.
Fixing it by supporting AV wwm-spill pseudos as well.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D155646