[all-commits] [llvm/llvm-project] 3c2a66: [RISCVInsertVSETVLI] Generalize scalar extract (vm...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c2a66973e19c92659f1e52b28b824c57a6322c8
      https://github.com/llvm/llvm-project/commit/3c2a66973e19c92659f1e52b28b824c57a6322c8
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-16 (Wed, 16 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  Log Message:
  -----------
  [RISCVInsertVSETVLI] Generalize scalar extract (vmv.x.s, and vmx.f.s) hamdling

vmv.x.s and vmv.f.s are unconditional. They read the low element of a vector
register (not vector group), and function even when VL=0 or VSTART>0. As such,
they are don't care with respect to both VL and LMUL.

We'd previously had handling in the forward pass only via the NoRegister
mechanusm.  (The only instructions with SEW but without VL are these extracts.)
This patch moves that handling into getDemanded so that the backwards pass
benefits as well.

Differential Revision: https://reviews.llvm.org/D157991