[all-commits] [llvm/llvm-project] b06e52: [RISCVInsertVSETVLI] Default to VL=1 for scalar ex...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b06e52c32f4d6945b7ea8ac451d16be58ec455ce
      https://github.com/llvm/llvm-project/commit/b06e52c32f4d6945b7ea8ac451d16be58ec455ce
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-16 (Wed, 16 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/double_reduct.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
    M llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

  Log Message:
  -----------
  [RISCVInsertVSETVLI] Default to VL=1 for scalar extracts

We were defaulting to VL=0 when we didn't otherwise have a vsetv
nearby. Instead, let's use VL=1. VL=0 is very much a cornercase
in hardware, and let's avoid if we can.

Differential Revision: https://reviews.llvm.org/D158015