[all-commits] [llvm/llvm-project] b0a77a: [DAG] SimplifyDemandedBits - add sra(shl(x, c1), c1)...

Simon Pilgrim via All-commits all-commits at lists.llvm.org
Tue Aug 15 08:32:28 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0a77af4f19a4f6b49ac4aadd0a9c89d287b74ce
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-08-15 (Tue, 15 Aug 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/CodeGen/X86/packss.ll

  Log Message:
  [DAG] SimplifyDemandedBits - add sra(shl(x,c1),c1) -> sign_extend_inreg(x) demanded elts fold

Move the sra(shl(x,c1),c1) -> sign_extend_inreg(x) fold inside SimplifyDemandedBits so we can recognize hidden splats with DemandedElts masks.

Because the c1 shift amount has multiple uses, hidden splats won't get simplified to a splat constant buildvector - meaning the existing fold in DAGCombiner::visitSRA can't fire as it won't see a uniform shift amount.

I also needed to add TLI preferSextInRegOfTruncate hook to help keep truncate(sign_extend_inreg(x)) vector patterns on X86 so we can use PACKSS more efficiently.

Differential Revision: https://reviews.llvm.org/D157972

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