[all-commits] [llvm/llvm-project] 9f8dcb: [AArch64] Try to detect patterns with fdiv and fmu...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f8dcb070655b4914d47848dcfbba742f12b25bd
      https://github.com/llvm/llvm-project/commit/9f8dcb070655b4914d47848dcfbba742f12b25bd
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2023-08-15 (Tue, 15 Aug 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/svtcf-fmul-fdiv-combine.ll

  Log Message:
  -----------
  [AArch64] Try to detect patterns with fdiv and fmul for [su]cvtf.

If fmul's constant operand is the reciprocal of a power of 2 (i.e 1/2^n) or
fdiv's constant operand is power of 2, we can try to match patterns with
[su]int_to_fp for [su]cvtf.

Differential Revision: https://reviews.llvm.org/D156538