[all-commits] [llvm/llvm-project] ac00cc: [RISCV] Fix assertion when passing f64 vectors via...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac00cca3d9c6c3e9118ebbe47aa5b3ba1ee7404f
      https://github.com/llvm/llvm-project/commit/ac00cca3d9c6c3e9118ebbe47aa5b3ba1ee7404f
  Author: wangpc <wangpengcheng.pp at bytedance.com>
  Date:   2023-08-15 (Tue, 15 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/pr64645.ll

  Log Message:
  -----------
  [RISCV] Fix assertion when passing f64 vectors via integer registers

The vector arguments are split but assignments won't be pending.

Fixes #64645

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D157847