[all-commits] [llvm/llvm-project] 9f369a: [RISCV] Lower reverse shuffles of fixed i1 vectors...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f369a4c437fa3e78d09b1e0fd832a985f63e776
      https://github.com/llvm/llvm-project/commit/9f369a4c437fa3e78d09b1e0fd832a985f63e776
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-14 (Mon, 14 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

  Log Message:
  -----------
  [RISCV] Lower reverse shuffles of fixed i1 vectors to vbrev.v

If we can fit an entire vector of i1 into a single element, e.g. v32i1 ->
v1i32, then we can reverse it via vbrev.v.
We need to handle the case where the vector doesn't exactly fit into the larger
element type, e.g. v4i1 -> v1i8. In this case we shift up the reversed bits
afterwards.

Reviewed By: fakepaper56, 4vtomat

Differential Revision: https://reviews.llvm.org/D157614