[all-commits] [llvm/llvm-project] a3f275: [AArch64][GISel] Add handling for G_VECREDUCE_FMAX...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a3f2751f782f3cdc6ba4790488ec20163a40ac37
      https://github.com/llvm/llvm-project/commit/a3f2751f782f3cdc6ba4790488ec20163a40ac37
  Author: David Green <david.green at arm.com>
  Date:   2023-08-14 (Mon, 14 Aug 2023)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll
    A llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fminmax.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir
    M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll

  Log Message:
  -----------
  [AArch64][GISel] Add handling for G_VECREDUCE_FMAXIMUM and G_VECREDUCE_FMINIMUM

This is a lot of copy-pasting for the existing handling of
G_VECREDUCE_FMAX/G_VECREDUCE_FMIN to add handling for
G_VECREDUCE_FMAXIMUM/G_VECREDUCE_FMINIMUM in the same way.

Differential Revision: https://reviews.llvm.org/D156615