[all-commits] [llvm/llvm-project] d19947: [AArch64][GISel] Handling for G_VECREDUCE_FMIN and...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d199478af48ada4b7be7c4862b8782cb3093ad93
      https://github.com/llvm/llvm-project/commit/d199478af48ada4b7be7c4862b8782cb3093ad93
  Author: David Green <david.green at arm.com>
  Date:   2023-08-14 (Mon, 14 Aug 2023)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

  Log Message:
  -----------
  [AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX

This adds legalization for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX, where the
selection can go via tablegen patterns. I haven't tried to get non-power2 types
working yet, just the more legal types.

Differential Revision: https://reviews.llvm.org/D156614