[all-commits] [llvm/llvm-project] 6cb55a: [RISCV] Add Precommit test for D156685

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cb55a3d9a7a8d749f446fd7368f35e52a8b461f
      https://github.com/llvm/llvm-project/commit/6cb55a3d9a7a8d749f446fd7368f35e52a8b461f
  Author: LWenH <924105575 at qq.com>
  Date:   2023-08-13 (Sun, 13 Aug 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add Precommit test for D156685

Add baseline test for [[ https://reviews.llvm.org/D156685 | D156685 ]].

In LLVM, such signed 8 bits reaminder operation will first signed extened the operands to 32 bits, and then narrow the operands to the smaller bits data type such as 16 bits during the CorrelatedValuePropagation Pass to optimize the final data storage size.

Such a signed extension operation for srem in LLVM system is to prevent the Undefined Behavior.  Taking an example, -128 % -1 will lead to the Undefined Behaviour under the i8 type in LLVM IR, but this won't happen for i32, so such pattern cannot be eliminated in the platform-independent InstCombine Pass. The LLVM IR of these sext/trunc operations will be translated one by one during the RVV backend code generation process, and redundant vsetvli instructions will be inserted.

In fact, according to the RVV instruction manual, the vrem.vv instruction has already specified the final output value of this type of overflow operation. For example, the overflow operation of -128 % -1 will get 0 according to the RISC-V spec, so through this patch , I think we can optimize these redundant rvv code through the SDNode pattern match at the instruction selection phase.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157592


  Commit: 555e0305fda5a502f85045142fa2016743fd73f8
      https://github.com/llvm/llvm-project/commit/555e0305fda5a502f85045142fa2016743fd73f8
  Author: LWenH <924105575 at qq.com>
  Date:   2023-08-13 (Sun, 13 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

  Log Message:
  -----------
  [RISCV]  Match  ext + ext + srem + trunc to vrem.vv

This patch match the SDNode pattern:" trunc (srem(sext, ext))" to vrem.vv. This could remove the extra "vsext" ,"vnsrl" and the "vsetvli" instructions in the case like "c[i] = a[i] % b[i]", where the element types in the array are all int8_t or int16_t at the same time.

For element types like uint8_t or uint16_t, the "zext + zext + urem + trunc" based redundant IR have been removed during the instCombine pass, this is because the urem operation won't lead to the overflowed in the LLVM.  However, for signed types, the instCombine pass can not remove such patterns due to the potential for Undefined Behavior in LLVM IR. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this situation doesn't occur for i32.  To address this,  LLVM first signed extends the operands for srem to i32 to prevent the UB.

For RVV,  such overflow operations are already defined by the specification and yield deterministic output for extreme inputs. For example, based on the spec, for the i8 type, -128 % -1 actually have 0 as the output result under the overflowed situation. Therefore, it would be able to match such pattern in the instruction selection phase for the rvv backend rather than removing them in the target-independent optimization passes like instCombine pass.

This patch only handle the sign_ext circumstances for srem.  For more information about the C test cases compared with  GCC, please see : https://gcc.godbolt.org/z/MWzE7WaT4

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156685


Compare: https://github.com/llvm/llvm-project/compare/eeccbe1ec8d1...555e0305fda5