[all-commits] [llvm/llvm-project] c52d95: [AArch64][SVE] Add asm predicate constraint Uph

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c52d9509d40d3048914b144618232213e6076e05
      https://github.com/llvm/llvm-project/commit/c52d9509d40d3048914b144618232213e6076e05
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2023-08-11 (Fri, 11 Aug 2023)

  Changed paths:
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
    M llvm/docs/LangRef.rst
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

  Log Message:
  -----------
  [AArch64][SVE] Add asm predicate constraint Uph

Some instructions such as multi-vector LD1 only accept a range
of PN8-PN15 predicate-as-counter. This new constraint allows more
refined parsing and better decision making when parsing these
instructions from ASM, instead of defaulting to Upa which incorrectly
uses the whole range of registers P0-P15 from the register class PPR.

Differential Revision: https://reviews.llvm.org/D157517