[all-commits] [llvm/llvm-project] 5033ec: Revert "[tests] Fix gpu-to-cubin.mlir (NFC)"

Mehdi Amini via All-commits all-commits at lists.llvm.org
Wed Aug 9 19:37:44 PDT 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5033ec0a9e7cc176d42c0da0ef095e21170092f4
      https://github.com/llvm/llvm-project/commit/5033ec0a9e7cc176d42c0da0ef095e21170092f4
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir

  Log Message:
  -----------
  Revert "[tests] Fix gpu-to-cubin.mlir (NFC)"

This reverts commit 4434bc5508dfd448b7666b81a423dc7783f4a698.

It does not make sense to introduce more passes to fix a parsing issue.
More importantly: it didn't fix the test!


  Commit: 1b272d21c8162ff577d1c45d1f9320f3465db23c
      https://github.com/llvm/llvm-project/commit/1b272d21c8162ff577d1c45d1f9320f3465db23c
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
    M mlir/test/Integration/Dialect/Arith/CPU/test-wide-int-emulation-compare-results-i16.mlir
    M mlir/test/Integration/Dialect/Arith/CPU/test-wide-int-emulation-constants-i16.mlir
    M mlir/test/Integration/Dialect/LLVMIR/CPU/X86/test-inline-asm-vector.mlir
    M mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
    M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sm80-lt/sparse-matmul-2-4-lib.mlir
    M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-dot.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-mask-compress.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-rsqrt.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-vp2intersect-i32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-broadcast.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-compress.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-constant-mask.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-contraction.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-create-mask-v4i1.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-create-mask.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-expand.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-extract-strided-slice.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-flat-transpose-col.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-flat-transpose-row.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-fma.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-gather.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-index-vectors.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-insert-strided-slice.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-maskedload.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-maskedstore.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-matrix-multiply-col.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-matrix-multiply-row.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-f32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-outerproduct-i64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-print-fp.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-print-int.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-realloc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32-reassoc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64-reassoc.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-si4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-reductions-ui4.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-scan.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-scatter.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shape-cast.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shuffle.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-shuffle16x16.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-sparse-dot-matvec.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-sparse-saxpy-jagged-matvec.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/test-transpose.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
    M mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir
    M mlir/test/mlir-cpu-runner/X86Vector/math-polynomial-approx-avx2.mlir
    M mlir/test/mlir-cpu-runner/math-polynomial-approx.mlir
    M mlir/test/mlir-cpu-runner/test-expand-math-approx.mlir
    M mlir/test/python/dialects/vector.py

  Log Message:
  -----------
  Revert "[mlir][VectorOps] Use SCF for vector.print and allow scalable vectors"

This reverts commit 490dae26cb3bee2e8401e4c2a7ad3e0996be67d0.

Bot is broken, seems like there is a problem of ambiguity in the parser.


  Commit: 363b655920c49a4bcb0869f820ed40aac834eebd
      https://github.com/llvm/llvm-project/commit/363b655920c49a4bcb0869f820ed40aac834eebd
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M flang/lib/Optimizer/Dialect/FIROps.cpp
    M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
    M flang/test/Fir/convert-to-llvm.fir
    M mlir/docs/PatternRewriter.md
    M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
    M mlir/include/mlir/IR/OpBase.td
    M mlir/include/mlir/IR/OpDefinition.h
    M mlir/lib/Bindings/Python/IRCore.cpp
    M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
    M mlir/lib/Dialect/Async/IR/Async.cpp
    M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
    M mlir/lib/Dialect/SCF/IR/SCF.cpp
    M mlir/lib/Rewrite/ByteCode.cpp
    M mlir/test/Bytecode/operand_segment_sizes.mlir
    M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
    M mlir/test/Dialect/GPU/invalid.mlir
    M mlir/test/Dialect/LLVMIR/invalid.mlir
    M mlir/test/Dialect/Linalg/named-ops.mlir
    M mlir/test/Dialect/OpenMP/invalid.mlir
    M mlir/test/Dialect/OpenMP/ops.mlir
    M mlir/test/Dialect/PDL/invalid.mlir
    M mlir/test/Dialect/PDLInterp/invalid.mlir
    M mlir/test/Dialect/SCF/invalid.mlir
    M mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
    M mlir/test/Dialect/Transform/ops-invalid.mlir
    M mlir/test/IR/parser.mlir
    M mlir/test/IR/traits.mlir
    M mlir/test/Rewrite/pdl-bytecode.mlir
    M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
    M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
    M mlir/test/Target/LLVMIR/omptarget-region-llvm.mlir
    M mlir/test/Target/LLVMIR/omptarget-region-parallel-llvm.mlir
    M mlir/test/Target/LLVMIR/openmp-llvm.mlir
    M mlir/test/Transforms/canonicalize-block-merge.mlir
    M mlir/test/Transforms/sccp.mlir
    M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
    M mlir/test/mlir-tblgen/op-decl-and-defs.td
    M mlir/test/mlir-tblgen/op-python-bindings.td
    M mlir/test/python/dialects/linalg/ops.py
    M mlir/test/python/dialects/ods_helpers.py
    M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
    M mlir/tools/mlir-tblgen/OpFormatGen.cpp
    M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
    M mlir/unittests/IR/AdaptorTest.cpp

  Log Message:
  -----------
  Finish renaming getOperandSegmentSizeAttr() from `operand_segment_sizes` to `operandSegmentSizes`

This renaming started with the native ODS support for properties, this is completing it.

A mass automated textual rename seems safe for most codebases.
Drop also the ods prefix to keep the accessors the same as they were before
this change:
 properties.odsOperandSegmentSizes
reverts back to:
 properties.operandSegementSizes

The ODS prefix was creating divergence between all the places and make it harder to
be consistent.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D157173


Compare: https://github.com/llvm/llvm-project/compare/460868611118...363b655920c4

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