[all-commits] [llvm/llvm-project] b80864: [mlir][LLVM] Delay debug intrinsic import to ensur...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b808648ac1308cc2563fdc1fc7796da704dc1ce5
      https://github.com/llvm/llvm-project/commit/b808648ac1308cc2563fdc1fc7796da704dc1ce5
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
    M mlir/lib/Target/LLVMIR/ModuleImport.cpp
    M mlir/test/Target/LLVMIR/Import/debug-info.ll
    M mlir/test/Target/LLVMIR/Import/import-failure.ll

  Log Message:
  -----------
  [mlir][LLVM] Delay debug intrinsic import to ensure dominance

This commit ensures that debug intrinsics are imported after all other
instructions of a function were imported.

Debug intrinsics in LLVM are excluded from the define-before-use
invariant, i.e., they can reference SSA values that do not dominate
them. So far, we had implemented checks to stop the import of such
intrinsics, but there were always additional cases that were not
covered (the latest being terminators that define such used values).

Reviewed By: gysit, zero9178

Differential Revision: https://reviews.llvm.org/D157496